The increasing demand for secure and efficient digital signal processing (DSP) in embedded systems has intensified the need for hardware platforms capable of delivering real-time performance without compromising cryptographic robustness. Field-Programmable Gate Arrays (FPGAs) have emerged as a versatile solution, offering fine-grained parallelism, low-latency execution, and reconfigurable logic for integrating both signal processing and cryptographic functions. This review presents a comprehensive synthesis of recent advancements in FPGA-based secure DSP architectures, encompassing classical primitives such as AES and ECC, as well as post-quantum cryptographic algorithms like Kyber, Dilithium, and NTRU. It explores design methodologies ranging from Register Transfer Level (RTL) to High-Level Synthesis (HLS), evaluating trade-offs in power, area, and latency, and detailing hardware-level countermeasures against side-channel attacks. Practical applications are surveyed across domains including healthcare, defense, secure communications, and multimedia processing, with comparative benchmarking on major Xilinx and Intel FPGA platforms. The review identifies key challenges, such as resource constraints, cross-platform portability, and the real-time implementation of cryptographic workloads, and highlights the integration of AI-based threat detection using models like convolutional and graph neural networks. A classification of machine learning applications in secure DSP is provided to contextualize current research directions. Finally, emerging trends are discussed, including post-quantum secure DSP systems, FPGA–AI co-acceleration, secure and reconfigurable hardware architectures, processing-in-memory (PIM), and heterogeneous platforms combining RISC-V SoCs with FPGA fabrics. By bridging cryptographic assurance with signal integrity, this work offers a holistic overview of the secure embedded computing landscape and a roadmap for future innovation at the intersection of signal processing, reconfigurable computing, and hardware-level security.