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PUBLISHED PAPERS
open access
Classifying FPGA Technology in Digital Signal Processing: A review
Minimum FPGA
;
digital signal processing
;
DSP algorithms
;
reconfigurability
;
parallel processing
;
digital filtering
;
FFT
;
communication systems
;
power optimization
.
By
Saman Sadeghi
a *
×
Mr. Saman Sadeghi
[email protected]
, Department Of Electrical Engineering-electronics, Mazandaran University Of Science And Technology, Babol, Iran, Iran
Journals
IJETS
2025, 1-46
Secure and Efficient Signal Processing on FPGA: A Comprehensive Review of Cryptographic, Post-Quantum, and AI-Enhanced DSP Implementations for Embedded Systems
IJETS
2025, 1-58
A Comprehensive Review of Digital Signal Processing (DSP) Algorithms and Their Applications in Telecommunication and Wireless Communication Systems
IJETS
2025, 1-49
A Comprehensive Review of Analog and Digital Filter Design: FPGA-Based Implementations, Real-Time Challenges, and Emerging Applications
IJETS
2023, 1-10
An intelligent algorithm based on wavelet and linear discriminant analysis for classification of motor imagery right/left hand movement by brain signal
IJETS
2024, 1-10
Classifying FPGA Technology in Digital Signal Processing: A review
Conference
IJETS
2024
, 2024
(), 1-10
open access
A Comprehensive Review of Analog and Digital Filter Design: FPGA-Based Implementations, Real-Time Challenges, and Emerging Applications
Digital Signal Processing (DSP)
;
Filter Design
;
Analog Filters (Butterworth
;
Chebyshev
;
Elliptic)
;
Digital Filters (FIR
;
IIR)
;
Machine Learning
;
Neural Networks
;
Reinforcement Learning
;
Quantum-Inspired Algorithms
;
Field-Programmable Gate Arrays (FPGA)
;
Real-Time Systems
;
Adaptive Filtering
;
Edge Computing
;
Secure Signal Processing
;
Reconfigurable Architectures
;
Neuromorphic Architectures
;
Internet of Things (IoT)
.
By
Saman Sadeghi
×
Mr. Saman Sadeghi
[email protected]
, Department Of Electrical Engineering-electronics, Mazandaran University Of Science And Technology, Babol, Iran, Iran
Journals
IJETS
2025, 1-46
Secure and Efficient Signal Processing on FPGA: A Comprehensive Review of Cryptographic, Post-Quantum, and AI-Enhanced DSP Implementations for Embedded Systems
IJETS
2025, 1-58
A Comprehensive Review of Digital Signal Processing (DSP) Algorithms and Their Applications in Telecommunication and Wireless Communication Systems
IJETS
2025, 1-49
A Comprehensive Review of Analog and Digital Filter Design: FPGA-Based Implementations, Real-Time Challenges, and Emerging Applications
IJETS
2023, 1-10
An intelligent algorithm based on wavelet and linear discriminant analysis for classification of motor imagery right/left hand movement by brain signal
IJETS
2024, 1-10
Classifying FPGA Technology in Digital Signal Processing: A review
Conference
IJETS
2025
, 2025
(), 1-49
open access
A Comprehensive Review of Digital Signal Processing (DSP) Algorithms and Their Applications in Telecommunication and Wireless Communication Systems
Digital Signal Processing (DSP)
;
Telecommunication Systems
;
Wireless Communication
;
5G
;
Artificial Intelligence
;
Deep Reinforcement Learning (DRL)
;
Neural Architecture Search (NAS)
;
Graph Neural Networks (GNN)
;
Bayesian Optimization (BO)
;
Quadrature Amplitude Modulation (QAM)
;
Orthogonal Frequency Division Multiplexing (OFDM)
;
Channel Estimation
;
MIMO
;
Beamforming
;
Software-Defined Radio (SDR)
;
Edge Computing
;
Internet of Things (IoT)
;
FPGA
;
ASIC
;
Hardware Acceleration
;
Real-Time Systems
;
Adapti
.
By
Saman Sadeghi
×
Mr. Saman Sadeghi
[email protected]
, Department Of Electrical Engineering-electronics, Mazandaran University Of Science And Technology, Babol, Iran, Iran
Journals
IJETS
2025, 1-46
Secure and Efficient Signal Processing on FPGA: A Comprehensive Review of Cryptographic, Post-Quantum, and AI-Enhanced DSP Implementations for Embedded Systems
IJETS
2025, 1-58
A Comprehensive Review of Digital Signal Processing (DSP) Algorithms and Their Applications in Telecommunication and Wireless Communication Systems
IJETS
2025, 1-49
A Comprehensive Review of Analog and Digital Filter Design: FPGA-Based Implementations, Real-Time Challenges, and Emerging Applications
IJETS
2023, 1-10
An intelligent algorithm based on wavelet and linear discriminant analysis for classification of motor imagery right/left hand movement by brain signal
IJETS
2024, 1-10
Classifying FPGA Technology in Digital Signal Processing: A review
Conference
IJETS
2025
, 2025
(), 1-58
open access
Secure and Efficient Signal Processing on FPGA: A Comprehensive Review of Cryptographic, Post-Quantum, and AI-Enhanced DSP Implementations for Embedded Systems
FPGA
;
Digital Signal Processing (DSP)
;
Cryptographic Primitives
;
Embedded Systems
;
Post-Quantum Security (PQC)
;
Side-Channel Attacks
;
High-Level Synthesis (HLS)
;
AES
;
RISC-V
;
Real-Time Processing
;
AI-Based Intrusion Detection
;
Reconfigurable Architectures
;
Lightweight Cryptography
;
Signal Authentication
;
FPGA-as-a-Service
;
Processing-in-Memory (PIM)
.
By
Saman Sadeghi
×
Mr. Saman Sadeghi
[email protected]
, Department Of Electrical Engineering-electronics, Mazandaran University Of Science And Technology, Babol, Iran, Iran
Journals
IJETS
2025, 1-46
Secure and Efficient Signal Processing on FPGA: A Comprehensive Review of Cryptographic, Post-Quantum, and AI-Enhanced DSP Implementations for Embedded Systems
IJETS
2025, 1-58
A Comprehensive Review of Digital Signal Processing (DSP) Algorithms and Their Applications in Telecommunication and Wireless Communication Systems
IJETS
2025, 1-49
A Comprehensive Review of Analog and Digital Filter Design: FPGA-Based Implementations, Real-Time Challenges, and Emerging Applications
IJETS
2023, 1-10
An intelligent algorithm based on wavelet and linear discriminant analysis for classification of motor imagery right/left hand movement by brain signal
IJETS
2024, 1-10
Classifying FPGA Technology in Digital Signal Processing: A review
Conference
IJETS
2025
, 2025
(), 1-46
open access
A Hardware Implementation of Twine Block Cipher High Level Synthesis Approach
Lightweight Cryptography
;
Twine Algorithm
;
High Level Synthesis
;
Field Programmable Gate Array (FPGA)
.
By Ali Nemati
a&b
,
Arash Ahmadi
*a&b
,
×
[email protected]
Journals
IJETS
2015
, 3
(1), 13-21
A Hardware Implementation of Twine Block Cipher High Level Synthesis Approach
Conference
Vahab Al
a&b
IJETS
2015
, 3
(1), 13-21